1 of 10 features ? 10 years minimum data retention in the absence of external power ? data is automatically protected during power loss ? replaces 32k x 8 volatile static ram, eeprom or flash memory ? unlimited write cycles ? low - power cmos ? read and writ e access times of 70 ns ? lithium energy source is electrically disconnected to retain freshness until power is applied for the first time ? full 10% v cc operating range (ds1230y) ? optional 5% v cc operating range (ds1230ab) ? optional industrial temperature range of -40 c to +85 c, designated ind ? jedec standard 28- pin dip package ? powercap module (pcm) package - directly surface -mountable module - replaceable snap -on powercap provides lithium backup battery - standardized pinout for all nonvolatile sram products - detachment feature on powercap allows easy removal using a regular screwdriver pin assignment pin description a0 - a14 - address inputs dq0 - dq7 - data in/data out ce - chip enable we - write enable oe - output enable v cc - power (+5v) gnd - ground nc - no connect ds1230y/ab 256k nonvolatile sram www.maxim - ic.com 13 1 2 3 4 5 6 7 8 9 10 11 12 14 27 28 - pin encapsulated package 740 - mil extended a14 a7 a5 a4 a3 a2 a1 a0 dq1 dq0 v cc we a13 a8 a9 a11 oe a10 ce dq7 dq5 dq6 28 26 25 24 23 22 21 20 19 18 17 15 16 a12 a6 dq2 gnd dq4 dq3 1 nc 2 3 nc nc nc v cc we oe ce dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 gnd 4 5 6 7 8 9 10 11 12 13 14 15 16 17 nc a14 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 34 nc gnd v bat 34- pin p ower c ap module (pcm) (u ses ds9034pc + or ds9034pci+ p ower c ap ) 19 - 563 5 ; rev 11/10 downloaded from: http:///
ds1230y/ab 2 of 10 description the ds1230 256k nonvolatile srams are 262,144 - bit, fully static, nonvolatile srams organized as 32,768 words by 8 bits. each nv sram ha s a self - contained lithium energy source and control circuitry which constantly monitors v cc for an out -of- tolerance condition. when such a condition occurs, the lithium energy source is automatically switched on and write protection is uncondition ally en abled to prevent data corruption. dip - package ds1230 devices can be used in place of existing 32k x 8 static rams directly conforming to the popular bytewide 28 - pin dip standard. the dip devices also match the pinout of 28256 eeproms, allowing direct substitution while enhancing performance. ds1230 de vices in the low profile module package are specifically designed for surface - mount applications. there is no limit on the number of write cycles that can be executed and no additional support circuitry is r equired for microprocessor interfacing. read mode the ds1230 devices execute a read cycle whenever we (write enable) is inactive (high) and ce (chip enable) and oe (output enable) are active (low). the unique address specified by the 15 address inputs (a 0 - a 14 ) defines which of the 32,768 bytes of data is to be accessed. valid data will be ava ilable to the eight data output drivers within t acc (access time) after the last address input signal is stable, providing that ce and oe (output enable) access times are also satisfied. if oe and ce access times are not satisfied, then data access must be measured from the later - occurring signal ( ce or oe ) and the limiting parameter is either t co for ce or t oe for oe rather than address access. write mode the ds1230 devices execute a write cycle whenever the we and ce signals are active (low) after address inputs are stable. the later - occurring falling edge of ce or we will determine the start of the write c ycle. the write cycle is terminated by the earlier rising edge of ce or we . all address inputs must be kept valid throughout the write cycle. we must return to the high state for a minimum reco very time (t wr ) before another cycle can be initiated. the oe control signal should be kept inactive (high) during write cycles to avoid bus contention. however, if the output drivers are enabled ( ce and oe active) then we will disable the outputs in t odw from its falling edge. data retention mode the ds1230ab provides full functional capability for v cc greater than 4.75 volts and write protects by 4.5 volts. the ds1230y provides full functional capability for v cc greater than 4.5 volts and write protects by 4.25 volts. data is maintained in the absence of v cc without any additional support circuitry. the nonvolatile static rams constantly monitor v cc . should the supply vol tage decay, the nv srams automatically write protect themselves, all inputs become dont care, and all outp uts become high - impedance. as v cc falls below approximately 3.0 volts, a power switching circuit connects the lit hium energy source to ram to retai n data. during power - up, when v cc rises above approximately 3.0 volts the power switching circuit connects external v cc to ram and disconnects the lithium energy source. normal ram operation can resume after v cc exceeds 4.75 volts for the ds1230ab and 4.5 volts for the ds1230y. freshness seal each ds1230 device is shipped from maxim with its lithium energy source disconnected, guaranteeing full energy capacity. when v cc is first applied at a level greater than 4.25 volts, the lithium energy source is enabled for battery back-up operation. downloaded from: http:///
ds1230y/ab 3 of 10 packages the ds1230 devices are available in two packages: 28 - pin dip and 34 - pin powercap module (pcm). the 28 - pin dip integrates a lithium battery, an sram memory and a nonvolatile control func tion into a single package with a jedec - standard, 600 - mil dip pinout. the 34 - pin powercap module integrates sram memory and nonvolatile control along with contacts for connection to the lithium ba ttery in the ds9034pc powercap. the powercap module package design allows a ds1230 pcm device to b e surface mounted without subjecting its lithium backup battery to destructive high - temperature reflow soldering. after a ds1230 pcm is reflow soldered, a ds9034pc powercap is snapped on top of t he pcm to form a complete n onvolatile sram module. the ds9034pc is keyed to prevent improper attachment. ds1230 powercap modules and ds9034pc powercaps are ordered separately and s hipped in separate containers. see the ds9034pc data sheet for further information. downloaded from: http:///
ds1230y/ab 4 of 10 absolute maximum ratings voltage on any pin relative to ground -0.3v to +6.0v operating temperature range commercial: 0c to +70c industrial: -40c to +85c storage temperature range edip -40c to +85c powercap -55c to +125c lead temperature (soldering, 10s) +260c note: edip is wave or hand soldered only. soldering temperature (reflow, powercap) +260c this is a stress rating only and functional operation of the device at these or any other condi tions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating condi tions for extended periods of time ma y affect reliability. recommended dc operating conditions (t a : see note 10) parameter symbol min typ max units notes ds1230ab power supply voltage v cc 4.75 5.0 5.25 v ds1230y power supply voltage v cc 4.5 5.0 5.5 v logic 1 v ih 2.2 v cc v logic 0 v il 0.0 0.8 v dc electrical characteristics (v cc = 5v 5% for ds1230ab) (t a : see note 10) (v cc = 5v 10% for ds1230y) parameter symbol min typ max units notes input leakage current i il -1.0 +1.0 a i/o leakage current ce v ih v cc i io -1.0 +1.0 a output current @ 2.4v i oh -1.0 ma output current @ 0.4v i ol 2.0 ma standby current ce =2.2v i ccs1 200 600 a standby current ce =v cc -0.5v i ccs2 50 150 a operating current i cco1 85 ma writ e protection voltage (ds1230ab) v tp 4.50 4.62 4.75 v write protection voltage (ds1230y) v tp 4.25 4.37 4.5 v capacitance (t a = + 25 c) parameter symbol min typ max units notes input capacitance c in 5 10 pf input/output capacitance c i/o 5 10 pf downloaded from: http:///
ds1230y/ab 5 of 10 ac electrical characteristics (v cc = 5v 5% for ds1230ab) (t a : see note 10) (v cc = 5v 1 0% for ds1230y) parameter symbol ds1230ab-70 ds1230y- 70 units notes min max read cycle time t rc 70 ns access time t acc 70 ns oe to output valid t oe 35 ns ce to output valid t co 70 ns oe or ce to output active t coe 5 ns 5 output high- z from deselection t od 25 ns 5 output hold from address change t oh 5 ns write cycle time t wc 70 ns write pulse widt h t wp 55 ns 3 address setup time t aw 0 ns write recovery time t wr1 t wr2 5 15 ns 12 13 output high- z from we t odw 25 ns 5 output active from we t oew 5 ns 5 data setup time t ds 30 ns 4 data hold time t dh1 t dh2 0 10 ns 12 13 downloaded from: http:///
ds1230y/ab 6 of 10 read cycle see note 1 write cycle 1 see notes 2, 3, 4, 6, 7, 8, and 12 downloaded from: http:///
ds1230y/ab 7 of 10 write cycle 2 see notes 2, 3, 4, 6, 7, 8, and 13 power - down/power - up condition see note 11 power - down/power - up timing (t a : see note 10) parameter symbol min typ max units notes v cc fail detect to ce and we inactive t pd 1.5 s 11 v cc slew fro m v tp to 0v t f 150 s v cc slew from 0v to v tp t r 150 s v cc valid to ce and we inactive t pu 2 ms v cc valid to end of write protection t rec 125 ms downloaded from: http:///
ds1230y/ab 8 of 10 (t a = + 25 c) parameter symbol min typ max units notes expected data retention time t dr 10 years 9 warning: under no circumstance are negative undershoots, of any amplitude, allowed when device is in batt ery backup mode. notes: 1. we is high for a read cycle. 2. oe = v ih or v il . if oe = v ih during write cycle, the output buffers remain in a high- impedance state. 3. t wp is specified as the logical and of ce and we . t wp is measured from the latter of ce or we going low to the earlier of ce or we going high. 4. t dh , t ds are measured from the earlier of ce or we going high. 5. these parameters are sampled with a 5 pf load and are not 100% tested. 6. if the ce low transition occurs simultaneously with or latter than the we low transition, the output buffers rema in in a high-impedance state during this period. 7. if the ce high transition occurs prior to or simultaneously with the we high transition, the output buffers remain in high-impedance state during this period. 8. if we is low or the we low transition occurs prior to or simultaneously with the ce low transition, the output buffers remain in a high-impedance state during this period. 9. each ds1230 has a built - in switch that disconnects the lithium source until the user first applies v cc . the expected t dr is defined as accumulative time in the absence of v cc starting from the time power is first applied by the user. this parameter is assured by component selecti on, process control, and design. it is not measured directly during production testing. 10. all ac and dc electrical characteristics are valid over the full operating temperatu re range. for commercial products, this range is 0 c to 70 c. for industrial produc ts (ind), this range is -40 c to +85 c. 11. in a power-down condition the voltage on any pin may not exceed the voltage on v cc . 12. t wr1 and t dh1 are measured from we going high. 13. t wr2 and t dh2 are measured from ce going high. 14. ds1230 modules are recognized by underwriters laborator ies (u l) under file e99151. dc test conditions ac test conditions outputs open output load: 100 pf + 1ttl gate cycle = 200 ns for operating current input pulse levels: 0 - 3.0v al l voltages are referenced to ground timing measurement reference levels input: 1.5v output: 1.5v input pulse rise and fall times: 5 ns downloaded from: http:///
ds1230y/ab 9 of 10 ordering information part temp range supply tolerance pin - package speed grade (ns) ds1230ab-70+ 0c to +70c 5v 5% 28 740 edip 70 ds1230abp-70+ 0c to +70c 5v 5% 34 powercap* 70 ds1230ab- 70ind+ -40c to +85c 5v 5% 28 740 edip 70 ds1230abp- 70ind+ -40c to +85c 5v 5% 34 powercap* 70 ds1230y-70+ 0c to +70c 5v 10% 28 740 edip 70 ds1230yp-70+ 0c to +70c 5v 10% 34 powercap* 70 ds1230y- 70ind+ -40c to +85c 5v 10% 28 740 edip 70 ds1230yp- 70ind+ -40c to +85c 5v 10% 34 powercap* 70 + denotes a lead (pb) -free/rohs-compliant package . * ds9034pc + or ds9034pci + (powercap) required. must be ordered separately. package information for the latest package outline information and land patterns, go to www.maxim - ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 28 edip mdt28+3 21-0245 34 pcap pc2+4 21-0246 downloaded from: http:///
ds1230y/ab 10 of 10 revision history revision date description pages changed 121907 added package information table ; removed the dip module package drawing and dimension table 9, 10 11/10 updated the storage information, soldering temperature, and lead temperature information in the absolute maximum ratings section; removed the -85, -100, -120, -150, and - 200 min/max information from the ac electrical characteristics table; updated the ordering information table (removed -85, -100, -120, -150, and - 200 parts and leaded -7 0 parts); removed the powercap module drawings and upd ated the package information table 1, 4, 5, 9 downloaded from: http:///
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